Field of the Invention
This invention relates generally to a logic circuit of the differential amplifier kind for performing logic operations on binary input signals and, more particularly, to a logic circuit particularly adapted for integrated circuit fabrication in which a separate reference voltage generating element is not required for the differential amplifier circuit.
Description of the Prior Art
The particular requirements of integrated circuit fabrication have forced changes in the design of various logic circuits from their original, discrete-component designs. For example, the constraints on such logic circuit designs placed by the integrated circuit fabrication techniques have resulted in the use of differential amplifiers and constant current sources as a fundamental building block for such logic circuits, and this kind of logic circuitry is typically referred to as emitter coupled logic (ECL). Representative of this technology is U.S. Pat. No. 3,259,761. Central to such ECL differential amplifier logic, is the requirement for a reference voltage generator to provide the necessary reference voltage against which the input signals are compared. Further, in order to provide high-speed logic circuits, the current that must flow through each logic circuit is necessarily large relative to the quiescent state, and accordingly the number of reference voltage generators must correspond roughly to the scale of the logic circuit, so that they are capable of absorbing the transient currents produced upon switching the various transistors making up the ECL logic circuit. Due to such reference voltage requirements, it is the commonly known technique to employ three transistors to realize a two-input OR gate in the ECL differential amplifier configuration.
Accordingly, the presently known conventional logic circuits have an inherent disadvantage in that they require a relatively large number of circuit elements. Moreover, because of the requirement to employ the reference voltage an additional wiring pattern for each logic circuit is required and a further disadvantage is present because the ratio of the area of the wiring pattern on the substrate is large, and this leads to corresponding increases in chip size.